Staff DFT Engineer

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The Opportunity

We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission‑critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

What You'll Do

• Act as a member of Alphawave central DFT methodology group responsible for developing, maintaining and supporting flows across all company business units and projects.
• Architect methodologies and flows for an integrated, RTL‑centric “shift‑left” DFT environment across company IPs, ASICs and SoC designs.
• Write and automate RTL for advanced DFT and DFD features not currently supported by the EDA vendors.
• Develop automated verification test bench and sequence creation for DFT IP. Architect end‑to‑end verification solutions from static design checks, through formal and sequence‑based verification.
• Build IP/block and SoC level scan insertion flows and scripting ATPG retargeting procedures. Create automated QoR checks for implementation quality control.
• Write static timing constraints, create waivers and devise flows for bullet‑proof timing checks.

What You'll Need

• Bachelor’s degree in Engineering Science, Electrical and Computer Engineering or Computer Science.
• 10+ years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles.
• Vast experience with various DFT EDA tools from Siemens, SNPS and Cadence.
• Good knowledge and understanding of Verilog/VHDL and SystemVerilog.
• Exposure to CAD and automation. Good exposure to using de‑Perl techniques in creating generic codes. Knowledge of TCL and Python is a plus.
• Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs).
• Track record in integrating custom‑made DFT logic for complex SoCs (System‑On‑Chip) and CoWoS (Chip‑On‑Wafer‑On‑Substrate) designs is highly desirable.
• Experience in SoC and IP/block level scan insertion and ATPG, simulation of zero delay and SDF‑annotated test sequences.

Salary and Benefits

Your contribution will be recognized with a base salary influenced by your qualifications, experience, location, and the internal equity of our team to ensure fairness and consistency across roles. In addition to our comprehensive benefits package, employees are also eligible for additional compensation opportunities, including Restricted Stock Units (RSUs), short‑term incentive program, Retirement & Savings Programs and participation in the Employee Stock Purchase Plan (ESPP).

• Health & Wellness programs that emphasize knowledge and prevention, helping you stay proactive and prepared to manage your health at every stage.
• Comprehensive health plans.
• Wellness Spending Account (WSA).
• Employee Assistance Program (EAP).

Time Off

• Paid Vacation.
• Paid Holidays.
• Parental Leave.

Equal Employment Opportunity Statement

Alphawave Semi is an equal‑opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.