Job Description
About Analog Devices
Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and.
Analog Devices’ Digital Business Unit (DBU) is seeking a Staff STA Engineer to lead timing sign-off and closure for complex mixed-signal SoCs manufactured on advanced process nodes and operating at high-speed clock rates. These SoCs integrate multiple processor cores and high-performance signal processing hardware. The role ensures that designs meet timing, signal integrity, and reliability requirements through advanced analysis and optimization techniques.
Key Responsibilities
Perform full-chip and block-level STA for multiple modes and corners. Analyze and resolve setup, hold, and clock domain crossing (CDC) issues. Create and validate timing constraints (SDC) for synthesis and P&R flows. Execute timing sign-off using industry-standard tools (e.g., PrimeTime, Tempus). Implement ECOs for timing fixes and validate changes. Collaborate with RTL, physical design, and DFT teams to ensure timing requirements are met. Develop automation scripts (TCL, Python, Perl) to streamline STA tasks and improve efficiency. Address challenges related to OCV, AOCV, POCV , and multi-voltage domains. Position Requirements
Education : B.Tech/M.Tech in Electrical/Electronics Engineering. Experience : 9–12 years in STA and physical design implementation for high-speed SoCs on advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm). Strong expertise in Static Timing Analysis , constraint development, and sign-off. Ability to innovate flows to meet QoR targets and ensure predictability. Good understanding of device/interconnect and circuit aspects of UDSM technologies. Proficiency in TCL, Python , or other scripting languages. Excellent communication skills and ability to work in a cross-functional global team . Experience with low-power design techniques (UPF/CPF). Familiarity with signal integrity and power integrity analysis . Knowledge of advanced process nodes and variation modeling . #LI-SM1
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days
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