Job Description

Hello Everyone,


We are looking for an engineer with strong experience in standard cell characterization.


Experience: 5+ Yrs

Notice Period: Immediate to 30 days


Key Responsibilities

  • Perform standard cell characterization for timing, power, and noise across PVT corners.
  • Characterize libraries using tools like Synopsys SiliconSmart, Liberty NCX, or Cadence Liberate.
  • Generate and validate models: .Lib, CCS, ECSM, NLDM, LVF.
  • Work on multi-voltage, multi-threshold (LVT, SVT, HVT) libraries.
  • Perform noise characterization (SI, Crosstalk, LVF).
  • Debug and resolve characterization issues related to:
  • Timing arcs
  • Constraint violations
  • Power modeling inconsistencies
  • Collaborate with Standard Cell Design, PDK, and STA teams for issue resolution.
  • Perform QA checks using Liberty Checker, ALF, or in-house scripts.
  • Support foundry sign-off requirements and customer deliverables.
  • Automate flows using Python / Perl / TCL / Shell scripting.


Required Skills & Qualifications

  • Hands-on experience with:
  • Synopsys SiliconSmart / Liberty NCX or Cadence Liberate
  • Advanced timing models: CCS, ECSM, LVF


Please share suitable profiles on this ID [email protected]/[email protected]

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