STA(Static Timing Analysis) Engineer

Experience: 5+years

Location: Bangalore

Job Description:

As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process corners.

Key Responsibilities:

• Own full-chip and block-level timing closure across RTL, synthesis, and physical implementation stages.
• Develop and validate timing constraints (SDC) for blocks, partitions, and full-chip designs.
• Perform timing analysis using industry-standard tools (e.g., PrimeTime, Tempus).
• Collaborate with design and architecture teams to define timing requirements and resolve timing violations.
• Analyze timing scenarios, margins, and corner cases.
• Integrate third-party...