Technologist, ASIC Development Engineering (Design Lead - High-speed IO)

<b>Job Description</b><br /> <ul> <li>Will be part of team responsible for IO and high speed interface solutions for next generation SOCs in advanced CMOS technology nodes.<br /> </li> </ul> Will architect IO and high speed interface solutions for SanDisk ASIC controllers.<br /> <br /> Will interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-TapeOut activities such as Silicon characterization .<br /> <br /> Provide good technical leadership in problem solving, planning and mentoring junior engineers.<br /> <br /> Propose innovative design solutions and design methodologies. Help in building a team and developing processes.<br /> <br /> <b>Qualifications</b><br /> <br /> Must have<br /> <ul> <li>Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering</li> <li>Working experience (10+ years) in IO including 3-5 years as project leaders</li> <li>Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization</li> <li>Should have hands-on experience in TX and RX design architectures for high speed applications such as DDR4/DDR5/HBM/UCIe along with timing budget analysis.</li> <li>Should be experienced in high speed design architectures such as SERDES, Equalization schemes</li> <li>Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc</li> <li>Should have extensive experience in ESD circuits design, Associated ESD guidelines and recommendations in different process nodes, IO and SOC level ESD review and signoff</li> <li>Experience in full custom high speed data path design such as DDR/HBM/UCIe PHY will be of advantage.</li> <li>Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies</li> <li>Experience in Mixed-mode simulation and analog/digital co-simulation will be of added advantage.</li> <li>Experience in creating EDA model such as Verilog model, Liberty etc will be of added advantage.</li> <li>Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 16nm and the associated DSM issues.</li> <li>Very analytical in nature and able to work in a multi-disciplinary environment</li> <li>Creative, out-of-the-box thinker with a high level of personal involvement</li> <li>Strong theoretical background with a pragmatic approach.</li> <li>Good verbal and written communication skills and experience working with different geographies.</li> <li>Good mentoring, documentation and presentation skills</li> </ul>