Test Engineer

My client is seeking a highly skilled and motivated
DFT (Design for Testability)
Engineer to join their team in Lausanne, Switzerland. This is an exciting opportunity for a professional with a strong background in DFT methodologies and a passion for innovation. The successful candidate will play a critical role in ensuring the testability and reliability of complex designs, contributing to the development of cutting-edge technology.

Responsibilities

As a DFT Engineer, your key responsibilities will include:

• Performing hierarchical MBIST and scan insertion, as well as BSD implementation
• Generating ATPG patterns, conducting coverage analysis, and achieving high coverage metrics
• Simulating patterns with timing and defining test mode timing constraints
• Analysing timing reports and ensuring timing convergence
• Developing cycle-accurate functional patterns using IJTAG methodology
• Collaborating closely with test and production engineering teams to debug and bring up devices at probe and final test stages
• Debugging silicon issues and providing effective solutions

Experience:

• A minimum of
  5 years of experience in DFT
  , including implementation, test pattern development, and simulation
• Proven expertise in contributing to DFT solutions for complex designs
• Hands-on experience with IJTAG methodologies
• Proficiency in hierarchical MBIST insertion, hierarchical scan insertion, and scan compression methodologies
• Experience in ATPG pattern generation for various fault models, fault coverage analysis, and achieving high coverage metrics
• Strong debugging capabilities for simulating patterns with timing
• Familiarity with industry-standard EDA tools for DFT, timing, and simulation
• Knowledge of System Verilog.

Education:

• A Bachelor's degree or higher in Electronics and Electrical Engineering, Computer Engineering, or a related field