Job Description
Job Title: Verification Engineer
Work Location: Hyderabad
Experience: 5+ Years
Notice Period: Immediate (Max 15 Days)
Job Description:
We are looking for a Verification Engineer to work on IP-level functional and performance verification using a UVM-based environment. The role involves integrating SystemC models into UVM, performing functional and performance correlation with RTL, and debugging issues to support timely delivery of RTL-aligned models.
Required Skills
- 5+ years of experience in UVM based IP-level verification.
- Strong hands-on expertise in:
- SystemVerilog and UVM methodology
- RTL verification and debugging
- Solid understanding of digital design concepts and verification methodologies.
- Excellent communication and collaboration skills.
- Ownership mindset with a focus on quality and timely delivery.
Preferred Skills
- Experience with NOC Subsystem
- Good Knowledge of Memory Protocols DDR, LPDDR, HBM
- SystemC/TLM mo...
Work Location: Hyderabad
Experience: 5+ Years
Notice Period: Immediate (Max 15 Days)
Job Description:
We are looking for a Verification Engineer to work on IP-level functional and performance verification using a UVM-based environment. The role involves integrating SystemC models into UVM, performing functional and performance correlation with RTL, and debugging issues to support timely delivery of RTL-aligned models.
Required Skills
- 5+ years of experience in UVM based IP-level verification.
- Strong hands-on expertise in:
- SystemVerilog and UVM methodology
- RTL verification and debugging
- Solid understanding of digital design concepts and verification methodologies.
- Excellent communication and collaboration skills.
- Ownership mindset with a focus on quality and timely delivery.
Preferred Skills
- Experience with NOC Subsystem
- Good Knowledge of Memory Protocols DDR, LPDDR, HBM
- SystemC/TLM mo...
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