Verification Engineer - IP Functional & Performance Verification

Project Description:

• We are looking for a Verification Engineer to work on IP-level functional and performance verification using a UVM-based environment. The role involves integrating System C models into UVM, performing functional and performance correlation with RTL, and debugging issues to support timely delivery of RTL-aligned models.

Responsibilities:

* Develop and maintain UVM-based verification environments for complex IP blocks, ensuring comprehensive functional coverage.

* Create, execute, and debug testcases in System Verilog to validate RTL functionality and identify design issues early in the cycle.

* Analyze design specifications and define verification plans, coverage goals, and test strategies aligned with project requirements.

* Collaborate closely with design, architecture, and validation teams to drive resolution of functional bugs and ensure high-quality deliverables.

* Continuously improve verification workflows by enhancing testbench components, refining methodologies, and promoting best practices.

Mandatory Skills Description:

• * 5-8 years of experience in UVM-based IP-level verification.
• * Strong hands-on expertise in:
• * System Verilog and UVM methodology
• * RTL verification and debugging
• * Solid understanding of digital design concepts and verification methodologies.
• * Excellent communication and collaboration skills.
• * Ownership mindset with a focus on quality and timely delivery.

Languages:

• English: B2 Upper Intermediate