Job Description

LeadSoc Technologies is hiring design and verification Lead!



Experience: 8 years to 15 years

Notice Period: Immediate to 30 days



Responsibilities



  • DDR, DDR Phy interface experience
  • System Verilog assertions
  • Functional coverage
  • Strong in clock concepts



Qualifications


BE/MTech pass out



Required Skills



  • 8 to 15 years of experience
  • Experience in DDR, DDR Phy interface
  • Proficiency in System Verilog assertions
  • Knowledge of functional coverage
  • Strong understanding of clock concepts



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