Job Description
LeadSoc Technologies is hiring design and verification Lead!
Experience: 8 years to 15 years
Notice Period: Immediate to 30 days
Responsibilities
- DDR, DDR Phy interface experience
- System Verilog assertions
- Functional coverage
- Strong in clock concepts
Qualifications
Experience: 8 years to 15 years
Notice Period: Immediate to 30 days
Responsibilities
- DDR, DDR Phy interface experience
- System Verilog assertions
- Functional coverage
- Strong in clock concepts
Qualifications
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