Job Description
Job Description (Brief):
- Verify PCIe Gen5 / Gen6 / Gen7 IP/subsystem using System Verilog & UVM
- Strong understanding of PCIe protocol, LTSSM, TLP/DLLP, PIPE, link training & equalization
- Experience with high-speed protocols, error handling, power management, and compliance
- Develo...
- Verify PCIe Gen5 / Gen6 / Gen7 IP/subsystem using System Verilog & UVM
- Strong understanding of PCIe protocol, LTSSM, TLP/DLLP, PIPE, link training & equalization
- Experience with high-speed protocols, error handling, power management, and compliance
- Develo...
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