VLSI Verification Professional

Greetings from ACL Digital! We are expanding our Design & Verification teams and looking for skilled professionals across multiple DV roles.

Interested candidates can apply or refer friends by sharing resumes to [email protected] — referrals are most welcome.

JD 1 – Formal Verification Engineer

- 4–13 years of Formal Verification experience

- IP & SoC-level formal verification exposure

- Low-speed peripherals: I2C, SPI, UART, GPIO

- Strong in properties, assertions & proofs

Location: Bangalore | NP: 30 Days

JD 2 – Principal / Lead Design Verification Engineer

- 15+ years of DV experience in IP & SoC verification

- Strong Verilog, SystemVerilog & UVM expertise

- Own end-to-end DV: test p...