Principal Interconnect Micro Architect And Rtl Design Engineer Jobs in Santa Clara Ca
ethical AI opportunities in United States
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Micro-Architect / RTL Design - CPU, Principal
🏢 d-Matrix
📍 Santa Clara, California, United States
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ASIC Design Engineer, GPU/ML Shader Core
🏢 AMD
📍 Santa Clara, California, United States
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Principal Interconnect Micro-architect and RTL Design Engineer
🏢 Advanced Micro Devices , Inc.
📍 Santa Clara, CA, Santa Clara County, CA, United States
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ASIC Design Engineer - New College Grad 2026
🏢 NVIDIA
📍 Santa Clara, CA, United States
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Senior ASIC Design Engineer - Hardware
🏢 NVIDIA
📍 Santa Clara, CA, United States
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ASIC Design Engineer - Cache Controller
🏢 Apple
📍 Santa Clara, CA, United States
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ASIC Design Engineer - Cache Controller
🏢 Apple
📍 Santa Clara, CA, United States
A
CPU Power Management Microarchitect/RTL Engineer
🏢 Apple
📍 Santa Clara, CA, United States
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ASIC Design Engineer - Cache Controller
🏢 Apple
📍 Santa Clara, CA, United States
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GPU Design Engineer – Memory Hierarchy
🏢 Apple
📍 Santa Clara, CA, United States
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GPU Design Engineer – Memory Hierarchy
🏢 Apple
📍 Santa Clara, CA, United States
A
GPU Design Engineer – Memory Hierarchy
🏢 Apple
📍 Santa Clara, CA, United States
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GPU Design Engineer – Memory Hierarchy
🏢 Apple
📍 Santa Clara, CA, United States
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Senior Design for Debug Architect and Methodology Engineer
🏢 NVIDIA
📍 Santa Clara, CA, United States
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Senior ASIC Design Engineer, Hardware Compute Group
🏢 Confidential
📍 Cupertino, CA, Santa Clara County, CA, United States
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GPU Design Engineer – Memory Hierarchy
🏢 Apple
📍 Santa Clara, CA, United States
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GPU Design Engineer – Memory Hierarchy
🏢 Apple
📍 Santa Clara, CA, United States